This is my attempt to construct the smartest Verilog (other languages later) editor/IDE. These are some of the currently available features:
Smart auto-completion hints
CodeBrain will provide a list of hints for the given beginning of an identifier only if that identifier is appropriate at the current context. For examples, if mynumber is a register declared in line 12, it wont be suggested for completion in line 10.
In the example above, the module and endmodule keywords are constant, and the name is defined by the user. All 3 are mandatory. Typing mo will create a hint for auto-completion inserting the constant parts and selecting the user-defined part. No clicks required.
Creating an instance of a module is tedious and error prone. CodeBrain knows your modules and will hint the name after two characters, then create the instantiation with default connection names, and automatically select the name of the instance. No clicks required.
If a signal is being used without being defined, it is clearly marked by the editor. This allows for early detection of mistakes before they accumulate and become hard to track.
- Usage of a signal / module / function / task that has not been defined.
- Assignment to a signal of different width.
- Continuous assignment to a reg.
- Any syntax error.
Inline documentation (Not implemented yet)
Moving the cursor over an identifier automatically shows its type, width, etc.
More coming soon!